1. Field of the Invention
The present invention relates to a semiconductor device which is applied to a crystal oscillating circuit or the like, and which is provided with a metal layer that becomes a wire or a bonding pad.
2. Prior Art
In a conventional crystal oscillating circuit or the like, a wire or a bonding pad is formed as a metal region within the semiconductor device. FIG. 7 is a circuit diagram showing the configuration of a crystal oscillating circuit. In FIG. 7, symbol 10 indicates a semiconductor integrated circuit. Symbol 11 indicates a crystal oscillator. Symbol 12 indicates a variable capacitance diode. Symbols 23, 24 and 25 indicate bonding pads. Symbols 20, 37, 38 and 39 indicate resistors. Symbols 21 and 22 indicate capacitors. Symbols 30, 31, 32, 33, 34, 35 and 36 indicate parasitic capacitances. Symbol 40 indicates a transistor.
This crystal oscillating circuit is formed of semiconductor integrated circuit 10, crystal oscillator 11 and variable capacitance diode 12 which works on crystal oscillator 11 so as to make the oscillation frequency variable. Crystal oscillator 11 and variable capacitance diode 12 are connected to each other in series. Both ends of the series circuit of crystal oscillator 11 and variable capacitance diode 12 are connected to semiconductor integrated circuit 10 via bonding pads 23 and 25, respectively.
In addition, parasitic capacitances are added to the respective circuit elements of semiconductor integrated circuit 10 in a distributed manner. For example, parasitic capacitance 33 is added to bonding pad 23, parasitic capacitance 34 is added to resistor 37, parasitic capacitance 35 is added to resistor 38, parasitic capacitance 36 is added to resistor 39, parasitic capacitance 30 is added to resistor 20, parasitic capacitance 31 is added to capacitor 21, and parasitic capacitance 32 is added capacitor 22.
In FIG. 7, bonding pads 23, 24 and 25 are formed of metal layers, for example, and the structures of and the portions beneath these metal layers are the same. FIG. 8 shows the structure of and the portion beneath a metal layer. In addition, FIG. 9 shows the condition of a connection of parasitic capacitances that are added to the portion beneath a metal layer which forms a bonding pad.
FIG. 8 is a cross-sectional diagram showing a cross-section of a structure in the vicinity of a metal region of which the structure is the same for a wire and a bonding pad. In FIG. 8, symbol 53 indicates a P type semiconductor substrate made of a P type silicon substrate. One end of this P type semiconductor substrate 53 is grounded. Symbol 51 indicates an N type semiconductor (silicon) layer that has been epitaxially grown on P type semiconductor substrate 53. A diffusion layer for constructing a transistor in a crystal oscillating circuit, for example, is formed in this N type semiconductor layer 51. Symbol 52 indicates an element isolation layer made of P type diffusion layers that have been diffused from both sides, upper and lower, of N type semiconductor layer 51, in order to electrically isolate N type semiconductor layer 51. Symbol 55 indicates a metal layer of which the main component is aluminum, and which forms a wire or a bonding pad. Symbol 50 indicates an insulating film for insulating metal layer 55 from N type semiconductor layer 51 where a diffusion layer or the like has been formed. Insulating film 50 is formed of a silicon nitride film having a thickness of 15 nm, for example. Symbol 54 indicates an N type buried diffusion layer of which the impurity concentration is higher than that of N type semiconductor layer 51. After N type buried diffusion layer 54 has been formed on P type semiconductor substrate 53, N type semiconductor layer 51 is epitaxially grown. N type buried diffusion layer 54 is formed in order to lower the resistance component of N type semiconductor layer 51 that has been epitaxially grown, and, at the same time, in order to increase the withstand voltage between N type semiconductor layer 51 and P type semiconductor layer (element isolation layer 52 plus P type semiconductor substrate 53).
In the above described configuration, parasitic capacitances 30 to 36 are formed between capacitors 21 and 22 in FIG. 7 and the P type semiconductor substrate that forms semiconductor integrated circuit 10 in FIG. 7, as well as between resistors 20, 37, 38 and 39 and the P type semiconductor substrate.
Each parasitic capacitance 30 to 36 is, as shown in FIG. 9, formed of a parasitic capacitance 60 (capacitance value C1) between metal layer 55 that becomes a wire or a bonding pad and N type semiconductor layer 51, and of a parasitic capacitance 61 (capacitance value C2) in the junction between N type semiconductor layer 51 and P type semiconductor substrate 53. Here, an imaginary electrode A is connected to metal layer 55, and an imaginary electrode B is connected to N type semiconductor layer 51.
FIG. 9 is a diagram of an equivalent circuit, showing the condition of the connection of parasitic capacitances 60 and 61, which occur between the respective layers of FIG. 8. Parasitic capacitance 60 is a parasitic capacitance formed between metal layer 55 and N type semiconductor layer 51, which respectively make contact with the two surfaces of insulating film 50. Parasitic capacitance 61 is a parasitic capacitance formed between N type buried diffusion layer 54 plus N type semiconductor layer 51 and P type semiconductor substrate 53 plus element isolation layer 52.
An equivalent circuit of the portion between electrode A which is connected to metal layer 55 and P type semiconductor substrate 53 which is grounded has, as shown in FIG. 9, the configuration where parasitic capacitance 60 and parasitic capacitance 61 are connected in series between electrode A and the ground. Electrode B is connected to the connected portion between parasitic capacitance 60 and parasitic capacitance 61. Here, parasitic capacitance 60 is determined by the dielectric constant and the thickness of insulating film 50, and by the area of the border, and has a fixed value. On the other hand, parasitic capacitance 61 is determined by the thickness and the area of a depletion layer on the surface that makes contact with the diffusion layer. The thickness of this depletion layer fluctuates depending on the value of the voltage which is applied across the two surfaces of this depletion layer, and thus, the value of parasitic capacitance 61 fluctuates in accordance with the value of this voltage.
FIG. 10 shows the fluctuations of the voltages at electrodes A and B by taking the lapse of time from the time when a voltage is applied to electrode A of FIG. 9 along the lateral axis, and by taking the voltages at electrodes A and B of FIG. 9 along the longitudinal axis. In FIG. 10, waveform A1 shows the waveform of the voltage at electrode A of FIG. 9. That is to say, waveform A1 shows the waveform of the voltage at bonding pad 23 made of a metal layer in FIG. 7. Waveform B1 shows the waveform of the voltage at electrode B of FIG. 9. That is to say, waveform B1 shows the waveform of the voltage at the layer that corresponds to electrode B within the structure beneath resistor 38 in FIG. 7.
In the following, the waveforms of FIG. 10 are described in reference to the configuration of FIG. 7.
In FIG. 7, when a voltage from the voltage source is applied to bonding pad 24, the circuits that are connected to this bonding pad 24 operate, and a voltage that has been determined by the series of circuits is applied to resistor 38.
Waveform A1 shows the waveform of the voltage that is applied to bonding pad 23. That is to say, waveform A1 shows the manner in which the voltage that is applied to bonding pad 23 is shifted to a constant voltage value in a period of time that is no longer than 0.01 second, and at the same time, the oscillation waveform of approximately 13 MHz that has been generated by crystal oscillator 11 is maintained.
Waveform B1 shows the waveform of the voltage at electrode B. That is to say, waveform B1 shows the manner in which the voltage at electrode B1 reaches a predetermined voltage value in a period of time that is no longer than 0.01 second, and after that, gradually decreases. The voltage of waveform B1 decreases, and thereby, the value of parasitic capacitance 61, which is shown in FIG. 9, changes. The capacitance value between electrode A and the ground also fluctuates along with the fluctuation in the value of parasitic capacitance 61.
The fluctuation in the voltage of waveform B1 is more concretely described in the following, in reference to FIG. 9. When a voltage is applied to electrode A of FIG. 9, parasitic capacitance 60 and parasitic capacitance 61 are rapidly charged, and a voltage which is gained by dividing the voltage across electrode A and the ground in accordance with the values of parasitic capacitances 60 and 61 is outputted to electrode B. However, a microscopic amount of diffusion current in accordance with the concentration of the junction in parasitic capacitance 61 flows out of the junction in the direction toward the ground from electrode B, and therefore, the potential of electrode B decreases, along with the flow of this charge. It generally takes a time period of at least ten seconds or more before the potential of electrode B is lowered to the ground.
When the potential of electrode B decreases as described above in FIG. 9, the capacitance value of parasitic capacitance 61 changes, and so does the capacitance value between electrode A and the ground. As a result of this, the capacitance value that has been parasitically added to resistor 38 in FIG. 7 also changes. The oscillation frequency of crystal oscillator 11 changes along with the change in the parasitic capacitance value that is added to resistor 38.
Next, the value of this parasitic capacitance and the fluctuation in the oscillation frequency are described. In an example where the parasitic capacitance value is found through calculation from the areas occupied by and the materials of the respective structures of the semiconductor integrated circuit, the value of parasitic capacitance 60 in FIG. 9 is, for example, 1.18 pF. In addition, as for the value of parasitic capacitance 61, the value immediately after power on is, for example, 4 pF, while the value after ten seconds from power on changes to 5 pF. In this case, the capacitance value between electrode A and the ground is found in a manner where 0.9112 pF immediately after power on changes to 0.9547 pF after ten seconds. The ratio of this change in the capacitance value is 4.6%.
On the other hand, the frequency of the oscillation waveform at bonding pad 23 in FIG. 7 is measured in the manner where the frequency value fluctuates by 0.3 ppm ten seconds after power on. In an oscillator that outputs the signal that becomes the reference in a cellular phone, for example, the allowable fluctuation range of the frequency is plus/minus 0.2 ppm. Accordingly, the above described 0.3 ppm is a value on the borders of the standard.
In a conventional cellular phone, as shown in FIG. 7, an oscillating circuit is formed of semiconductor integrated circuit 10, crystal oscillator 11 and variable capacitance diode 12. In order to connect semiconductor integrated circuit 10 to crystal oscillator 11 or the like, it is necessary to make connections to crystal oscillator 11 or the like via bonding pads 23 and 25 within semiconductor integrated circuit 10.
However, as shown in FIG. 9, parasitic capacitances are added to the respective capacitors and resistors, and in addition, the values of the parasitic capacitances fluctuate along with a discharge. Such fluctuations in the parasitic values take a time period of no less than ten seconds after power on, and during this time, the oscillation frequency gradually changes in accordance with this fluctuation in the parasitic capacitance values. The range of the change in the frequency during this time period is 0.1 Hz to 10 Hz, and in some cases, this numeral value exceeds 0.3 ppm, which is an allowable value for the frequency fluctuation ten seconds after power on, and which is required for a cellular phone.